Cadence Design Systems has launched Cadence Cerebrus Intelligent Chip Explorer, a new machine learning (ML)-based tool that automates and scales digital chip design, enabling customers to achieve demanding chip design goals.

According to the company, the combination of Cerebrus and the Cadence RTL-to-signoff flow offers advanced chip designers, CAD teams and IP developers the ability to improve engineering productivity by up to 10X versus a manual approach while also realizing up to a 20% better power, performance and area (PPA).

The new tool is cloud enabled and utilizes highly scalable compute resources from leading cloud providers to meet design requirements across a wide range of markets including consumer, hyperscale computing, 5G communications, automotive and mobile.

Cerebrus provides customers with the following benefits: quickly finds flow solutions human engineers might not naturally try or explore, improving PPA and productivity; allows design learnings to be automatically applied to future designs, reducing the time to better results; lets a single engineer optimize the complete RTL-to-GDS flow automatically for many blocks concurrently, allowing full design teams to be more productive; and also provides scalable on-premises or cloud-based design exploration for faster flow optimization.

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